Integrated circuit device testing is a procedure which has been observed for many years in order to obtain as high a degree of quality control as possible for electronic devices. A tester typically includes a plurality of conductive traces formed on a load board associated with the tester apparatus. It is necessary to interconnect a lead, of a leaded device, or a pad, of a non-leaded device, to a corresponding trace on the load board in order to effectuate testing. A test socket having a plurality of contacts is interposed between the device under test and the load board in order to effectuate interconnection. One contact engages, at a front end, the lead or pad of a device under test with its corresponding trace on the load board.
Over the years, shape and construction of such contacts have evolved in response to the construction of test sockets, load boards, and architecture of devices to be tested. Formerly, it was considered necessary to have a wiping action at the various locations of engagement at the contact ends in order to provide a good transmission path. As technology has progressed, however, it has become apparent that less wiping action is necessary to maintain a good transmission path than what was formerly believed. Furthermore, it has become apparent that excessive wiping action damages component parts at the various points of engagement and significantly decreases the life of the test socket and tester load board. Consequently, various attempts have been made to minimize abrading of one surface relative to another. The current state of the art, however, has been unable to define a construction adequate to both maximize efficiency of the test socket and minimize abrasion and consequent deterioration of component parts.
It is to these problems and dictates of the prior art that the present invention is directed. Its advantages will become more apparent with reference to the Summary of the Invention, Detailed Description of the Invention, appended claims and accompanying drawing figures.